Extraction of SPICE Model for Double Gate Vertical MOSFET

Suseno, Jatmiko Endro and Ahmadi, Muhammad Taghi and Riyadi, Munawar A. and Ismail, Razali (2009) Extraction of SPICE Model for Double Gate Vertical MOSFET. In: Asia Modelling Symposium 2009 Third Asia International Conference on Modelling and Simulation, 25-26 and 29 May 2009, Bandung and Bali, Indonesia.

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Vertical MOSFETs device have one important disadvantage, which is higher overlap capacitances such as the separated gate-source and gate-drain parasitic capacitances (CGSO and CGDO), which is known to be most crucial to the high-frequency/speed performance but very hard to extract. In this paper presents parameter extraction techniques to create an extended BSIM model card of vertical p-MOSFETs for circuit simulation with SPICE can be accurately obtained for these overlap capacitances determination. This device was modeled as a subcircuit with any sub elements such as resistors, capacitors and diodes that capture the parasitic effects. The subcircuit was simplified in order to modeling in BSIM easily. The overlap capacitances of vertical p-MOSFET can be determined by using capacitance parameter extraction of quasi static small signal equivalent circuit. The result showed that gate-drain paracitic capacitance (CGDO) is larger than gate-source parasitic capacitance (CGSO)

Item Type:Conference or Workshop Item (Paper)
Subjects:T Technology > TK Electrical engineering. Electronics Nuclear engineering
Q Science > QC Physics
Divisions:Faculty of Science and Mathematics > Diploma in Instrumentasi and Electronics
Faculty of Science and Mathematics > Department of Physics
ID Code:52067
Deposited By:Mr Instrumentasi MIPA
Deposited On:01 Mar 2017 08:42
Last Modified:01 Mar 2017 08:42

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