Extraction of SPICE Model for Double Gate Vertical MOSFET

Abstract

Vertical MOSFETs device have one important disadvantage, which is higher overlap capacitances such as the separated gate-source and gate-drain parasitic capacitances (CGSO and CGDO), which is known to be most crucial to the high-frequency/speed performance but very hard to extract. In this paper presents parameter extraction techniques to create an extended BSIM model card of vertical p-MOSFETs for circuit simulation with SPICE can be accurately obtained for these overlap capacitances determination. This device was modeled as a subcircuit with any sub elements such as resistors, capacitors and diodes that capture the parasitic effects. The subcircuit was simplified in order to modeling in BSIM easily. The overlap capacitances of vertical p-MOSFET can be determined by using capacitance parameter extraction of quasi static small signal equivalent circuit. The result showed that gate-drain paracitic capacitance (CGDO) is larger than gate-source parasitic capacitance (CGSO)